The present invention relates to a processing apparatus having a pipeline structure, and more particularly to a processing apparatus having the function of effecting a logic test and/or a software test within the apparatus.
A processing apparatus having a pipeline structure is formed by serially coupling a plurality of pipeline stages. Each stage includes a data latch means (hereinafter called pipeline latch) and a processing means. Data to be processed is sequentially shifted via the respective pipeline latches during predetermined pipeline cycles. In a pipeline processing apparatus of a data flow execution model, data, input through terminals are accompanied by a processing command which is read out of an internal memory, and transferred through the pipeline latches. After the data are processed in each pipeline stage, the result is taken out of output terminals. The detailed structure of this model is described in U.S. patent application Ser. No. 436,130, filed on Oct. 22, 1982 and entitled "Data Processing Machine Suitable For High Speed Processing". This apparatus has many advantages. First of all, high speed processing can be expected because the respective pipeline stages can operate in parallel. Secondly, a multiprocessor system can be easily constructed by coupling the input terminals of one apparatus to the output terminals of another apparatus. Further, many kinds of programs can be processed by means of the same hardware architecture. Moreover, since the large-scale integrated circuit technique can be employed, at least one pipeline processing apparatus can be integrated on a single semiconductor chip.
However, only the processing result appears at the output terminals, and none of the intermediate data of the processing appear at the output terminals. More particularly, the input data set is processed by sequential circuits and/or combinational circuits in the pipeline stages and is set in an output latch as the final result. The output terminals are only coupled to this output latch. Therefore, it is very difficult to know the processing state within the pipeline latches or the logic operations in the respective pipeline stages from the output result. This means that the pipeline processing apparatus of the prior art cannot be easily monitored or tested. That is, in the prior art, when the expected output data is not obtained it cannot be determined whether the cause of the failure exists in the software or in the hardware. If a bug is present in the software, a long period of time is required for discovering the bug because it is difficult to trace the program and because it is difficult to maintain intermediate data for future analysis when a defect exists in the hardware, it takes a long period of time for analyzing which circuit is faulty. Therefore, there is a delay before the design can be changed to eliminate the problems encountered.
In a pipeline processing apparatus, there are many data sets whose contents are sequentially varied in the respective pipeline stages. In addition, loop processing is executed only within the apparatus, and intermediate data does not appear at the output terminals. Furthermore, data which is generated midway in the processing and subsequently disappears in the pipeline stages is not derived from the output terminals. Accordingly, so long as the states of the pipeline stages cannot be directly observed externally, it is difficult to improve the testability of the pipe line apparatus.
Moreover, in a conventional pipeline processing apparatus, processing is advanced at a pipeline cycle rate that is fixed by the hardware architecture, and a test is also executed at the pipeline cycle rate. Therefore, a more complex test requiring a long pipeline cycle is impossible. For example, an input of a long test pattern is not acceptable, because a long period of time is required to apply the test pattern to the pipeline stages. That is, the prior art pipeline processor has a shortcoming in that the pipeline cycle can not be controlled by an external control signal. Testing may be effected by connecting externally extending signal lines to each of the pipeline stages. However, in the case where the processing apparatus is formed on an LSI chip, the number of external terminals is limited by the chip size. Further, the package is enlarged in size by the increase of test terminals for the respective stages. In addition, the number of bits output data bits is reduced, and hence the effectiveness of the pipeline processing apparatus which has the advantage of high speed processing, would be lost.
As described above, although the prior art pipeline processing apparatus is favorable for high speed-processing and multi-processing, it was not easily tested for hardware failure; nor can the internal state or the intermediate processing data be readily observed.